The present invention is concerned with a method of manufacturing a semiconductor device including a system-on-chip (SOC), and more particularly with a method of manufacturing a system-on-chip (SOC) having a multiple gate system wherein MOSs (Metal Oxide Semiconductors) having a thick film gate insulating film and a thin film gate insulating film are placed in an adjacent circuit and an internal circuit, respectively.
With the progress of design and fabrication techniques for the IC (Integrated Circuit), extensive investigations have been, in recent years, conducted to develop what is called a system-on-chip (referred to as xe2x80x9cSOCxe2x80x9d, hereinafter) wherein components accommodating on a single chip thereof can fulfill a system function which has, hitherto, required a systematic organization with a plurality of LSIs (Large Scale Integrated circuits).
IPs (Intellectual Properties) which may be incorporated into a SOC include a CPU (Central Processing Unit), a logic circuit, various memories with high storage capacities, voice and image processing circuits, circuits for various interfaces, a digital-analog hybrid signal processing circuit and so forth, and functional blocks of these sorts constitute an internal circuit thereof.
Nevertheless, as a conventional LSI, a SOC is also provided with an adjacent circuit having a function of input-output protection or such for the purpose of protecting the internal circuit from the ESD (Electro-Static Discharge), the current noise and the like.
Such an internal circuit and an adjacent circuit as described above, each comprising numerous MOSs, constitute a multiple gate system. In general, a gate insulating film of a MOS contained in the internal circuit is made thin to be 3 nm or less so as to achieve a high integration of the internal circuit.
In contrast with this, for a MOS contained in the adjacent circuit, what is necessitated is a high withstand voltage to attain a sufficient capability of the input-output protection. A gate insulating film in the adjacent circuit is, therefore, required to have a satisfactory insulating effect so that the gate insulating film in the adjacent circuit is made to become a thicker film than the gate insulating film in the internal circuit.
In practice, a film thickness generally regarded as being sufficient for the gate insulating film in the adjacent circuit is 5 nm or less. However, when a strong insulating effect is specially called for due to the presence of a high voltage such as a supply voltage, the film thickness thereof is, in some cases, set to be at least 5 nm but not greater than 7 nm.
Consequently, for the successful development of the SOC, it is essential to be able to manufacture well, on one and the same chip, the multiple gate system, wherein MOSs having the thick film gate insulating film and the thin film gate insulating film are placed in the adjacent circuit and the internal circuit, respectively.
Satisfying this requirement is a matter of great importance in the SOC fabrication. This can be explained as follows. Since many functional blocks are incorporated into a SOC, the demand for a higher integration in its internal circuit is particularly strong and, to achieve this, the gate insulating film therein is made extremely thin. This creates a large difference in film thickness between the gate insulating film in the internal circuit and the gate insulating film in the adjacent circuit. Then, in manufacturing a SOC, numerous MOSs having gate insulating films of very different film thickness must be formed on one and the same chip.
An example of a conventional method of manufacturing such a multiple gate system wherein gate insulating films are made of silicon oxide films is shown schematically in FIG. 6. The drawings herein illustrate, in sequence, the steps of forming, on the left 501 of a field oxide film 503, a MOS contained in an internal circuit and, on the right 502 of the field oxide film, a MOS contained in an adjacent circuit.
First, as shown in FIG. 6(a), a field oxide film for element isolation is formed on a silicon substrate 504.
Next, as shown in FIG. 6(b), the entire surface of the silicon substrate is subjected to oxidation and thereby, as first gate insulating films, silicon oxide films 505 and 506 are grown in the internal circuit and adjacent circuit, respectively.
After that, the silicon oxide film 505 lying in the internal circuit alone is removed, which brings about a structure shown in FIG. 6(c). In the vicinity of the surface of the gate insulating film with which the adjacent circuit is to be formed, impurities 507 such as particles and organic substances are present. Although impurities are also present in the vicinity of the surface of the silicon substrate in a region where the internal circuit is to be formed, they are herein omitted from the drawing.
Because these impurities may cause a pattern defect, a poor withstand voltage for the gate insulating film or such, these impurities are removed in a cleaning step. The structure after the removal of impurities is shown in FIG. 6(d).
Subsequently, the entire surface of the silicon substrate is again subjected to oxidation and thereby, as second gate insulating films, silicon oxide films 509 and 510 are grown in the internal circuit and the adjacent circuit, respectively. As shown in FIG. 6(e), this results in formation of a double layer of silicon oxide films which is to be formed into a thick film gate insulating film of the adjacent circuit, along with formation of a single layer of silicon oxide film which is to be formed into a thin film gate insulating film of the internal circuit.
Following that, a polysilicon film is deposited on the silicon oxide films and this obtained polysilicon film is then formed into gate electrodes 511 and 512 by means of photolithography or the like. Thereafter source-drain regions 513 to 516 are formed, accomplishing a SOC which has a MOS with a thick film gate insulating film in the adjacent circuit and another MOS with a thin film gate insulating film in the internal circuit, as shown in FIG. 6(f).
With respect to a cleaning agent which is used to remove impurities present in the vicinity of the surface of the gate insulating film with which the adjacent circuit is formed, an APM cleaning solution or a mixed solution of ammonia, hydrogen peroxide and ultrapure water is hitherto utilized. In this instance, it is considered that the solution removes particles by the mechanisms of (a) a lifting-off effect on particles resulting from etching and oxidation repeatedly applied to the surface of the gate insulating film, (b) an inhibitory effect on particle reattachment to the substrate surface due to the generation of a repulsive force therebetween by making the xcex6 potential of removed particles equal to the potential of the substrate surface, and the like.
Therefore, in order to obtain a clean surface of the gate insulating film with which the adjacent circuit is formed, it was supposed that a thorough particle lifting-off must be performed, in other words, the surface must be etched a great deal. This has so far led to setting of a high cleaning temperature and a long cleaning time period. In some cases, an etching amount of the gate insulating film even exceeded 0.2 nm in terms of film thickness.
However, when cleaning is performed in such conditions, although the particles may be successfully removed, the surface roughness of the gate insulating film may increase, as depicted by a wavy line 508 in FIG. 6(d), and the reliability of the gate insulating film in the adjacent circuit may decrease.
Furthermore, even if another oxidation or the like is subsequently applied thereto, the gate insulating film with the degraded surface cannot recover its quality and may only produce a gate insulating film with a low reliability.
The prime factor for that is presumably the generation of the electric field centralizations brought about by the unevenness which arises locally on the interface between the gate insulating film and the gate electrode. This probably results in the TDDB (Time Dependent Dielectric Breakdown) and lowers the reliability of the gate insulating film.
Now, in Japanese Patent Application Laid-open No. 112454/1998, it was disclosed that an object of an invention therein is to reduce roughness which is produced by etching in cleaning the surface of a silicon semiconductor substrate. There is also described, in the publication, matters concerning the degradation of the gate insulating film.
However, nothing is described in respect of a thick film gate insulating film contained in the adjacent circuit of the SOC or the like. Moreover, regarding the cleaning conditions, such as the cleaning temperature and the cleaning time period, only general aspects are mentioned and the control made over the etching amount of the gate insulating film is not described. Therefore, in some cases, the evenness of the thick film gate insulating film of the SOC or the like, in particular, may not be steadily achieved thereby.
Further, in Japanese Patent Application Laid-open No. 110640/1988, aiming at improvement upon controllability of the cleaning, there is proposed that, in the cleaning step with an APM cleaning solution being used, the cleaning is performed at ambient temperature while applying ultrasonic waves.
In the publication, however, nothing is described in respect of a thick film gate insulating film contained in the adjacent circuit of the SOC or the like. Moreover, nothing is mentioned concerning either the control made over the etching amount of the gate insulating film or the surface roughness of the gate insulating film. Therefore, in some cases, the evenness of the thick film gate insulating film of the SOC or the like, in particular, may not be steadily achieved thereby.
Therefore, if any of the conventional techniques including the above examples is used, good evenness cannot be steadily achieved for the gate insulating film after the cleaning, particularly in a semiconductor device equipped with both of a MOS having a thick film gate insulating film and a MOS having a thin film gate insulating film, such as a SOC, and in such a case, high reliability cannot be secured for the thick film gate insulating film.
Accordingly, an object of the present invention is to attain a high reliability for a thick film gate insulating film of an adjacent circuit in a semiconductor device such as a SOC, which comprises the adjacent circuit in which a MOS having the thick film gate insulating film is placed and an internal circuit in which a MOS having a thin film gate insulating film is placed.
In order to achieve the object, the present invention provides a method of manufacturing a system-on-chip (SOC) comprising an adjacent circuit in which a MOS having a thick film gate insulating film made of layers of a first gate insulating film and a second gate insulating film is placed and an internal circuit in which a MOS having a thin film gate insulating film made of a second gate insulating film is placed; which comprises the steps of:
(a) forming the first gate insulating film on a silicon substrate;
(b) removing the first gate insulating film lying in a region where said internal circuit is to be formed;
(c) cleaning said silicon substrate under the conditions that an etching amount of the first gate insulating film lying in a region where said adjacent circuit is to be formed is, by the film thickness, not less than 0.01 nm but not greater than 0.2 nm; and
(d) forming the second gate insulating film on said silicon substrate.
Further, the present invention provides a method of manufacturing a semiconductor device wherein a first MOS and a second MOS having respective gate insulating films of different film thickness are laid on and incorporated into one and the same silicon substrate; which comprises the steps of:
(a) forming a first gate insulating film on said silicon substrate;
(b) removing the first gate insulating film lying in a region where said first MOS is to be formed;
(c) cleaning said silicon substrate under the conditions that an etching amount of the first gate insulating film lying in a region where said second MOS is to be formed is, by the film thickness, not less than 0.01 nm but not greater than 0.2 nm; and
(d) forming a second gate insulating film on said silicon substrate.
The present invention provides a method of manufacturing a SOC comprising an adjacent circuit in which a MOS having a thick film gate insulating film made of layers of a first gate insulating film and a second gate insulating film is placed and an internal circuit in which a MOS having a thin film gate insulating film made of a second gate insulating film is placed, wherein a silicon substrate is cleaned under the conditions that an etching amount of a first gate insulating film lying in a region where the adjacent circuit is to be formed is, by the film thickness, not less than 0.01 nm but not greater than 0.2 nm. Consequently, excellent evenness can be steadily achieved for the first gate insulating film, and therefore, the reliability of the thick film gate insulating film can be enhanced.